1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same. In particular, it relates to a semiconductor device provided with a local interconnection for making electrical connection among conductive regions and a method of manufacturing the same.
2. Description of the Prior Art
As the integration level of semiconductor devices including CMOS or Bi-CMOS circuits becomes high, silicide layers of titanium (Ti), cobalt (Co), nickel (Ni), platinum (Pt) and the like are generally utilized to form gate electrodes, source layers and drain layers for the purpose of reducing the parasitic resistances and the parasitic capacitances thereof.
Silicide layers can be formed by the salicide technique. Namely, after forming insulating sidewalls on the both sides of the gate electrodes, a metallic film is formed on the entirety of the transistor formation area, followed by reaction between the metallic film and silicon of the source electrode, the drain electrode and the gate electrode in order to form silicide layers respectively on the upper surface of the source electrode, the drain electrode and the gate electrode in a self-alignment manner. This method is described in U.S. Pat. No. 4,384,301.
Ti has been frequently utilized for formation of the silicide layer. It is known to introduce, nitrogen into the atmosphere for thermal treatment in order to form a silicide layer on the surface of the Ti film, as illustrated in U.S. Pat. No. 4,545,116. In accordance with this technique, a TiN film is successively formed after formation of a TiSi film in the nitrogen atmosphere and utilized for forming a local interconnection by making use of the TiN film, which is conductive and functions as a barrier layer for preventing impurity diffusion.
Local interconnection of this type are described also in U.S. Pat. No. 4,821,085, U.S. Pat. No. 4,804,636 and U.S. Pat. No. 4,657,628.
The advantages of a local interconnection have been frequently reported. For example, in U.S. Pat. No. 4,746,219, neighboring devices are connected by means of a local interconnection. Also, in U.S. Pat. No. 4,975,756, an SRAM is constructed by cross-coupling CMOS inverters by means of local interconnection. Furthermore, in U.S. Pat. Nos. 5,010,032 and 4,890,141, n-type and p-type polysilicon gate electrodes formed from a polysilicon layer are connected to each other by means of local interconnection in order to prevent two type impurities contained in the polysilicon layer from interdiffusion.
Meanwhile, when the TiN layer formed on the TiSi layer is utilized to form a fine local interconnection, the TiN layer has to be locally removed from the TiSi film, an oxide film or the like underlying surface by etching.
The removal of the unnecessary TiN film may be carried out, for example, by dry etching with a chlorine compound gas as illustrated in U.S. Pat. No. 4,793,896, U.S. Pat. No. 4,863,559 and U.S. Pat. No. 4,957,590 or by dry etching with a gas of freon system as illustrated in U.S. Pat. No. 4,675,073. However, in accordance with such etching, the selectivity ratio of TiN respective to the underlying surface made of TiSi or an oxide can not be sufficiently secured and often fluctuates during the etching process in any case of the conventional techniques.
In order to avoid the above problem, it has been proposed to switch the composition of the etchant gas in the middle of the etching process as described in U.S. Pat. No. 5,122,225. However, the control of the process becomes complicated to switch the composition of the etchant gas in the middle of the etching process, resulting in the need for a large process margin.
Also, an appropriate material for formation of a local interconnection can be selected in order to improve the selectivity ratio of TiN respective to the underlying silicide layer, as illustrated in U.S. Pat. No.4,980,020. In the description of the patent, a local interconnection is formed by forming the silicide layer with a different material by sputtering on the silicide layer.
When sputtering is utilized for the deposition of a local interconnection layer, the surface of the silicide layer has to be subjected to reverse RF sputtering etching treatment in order to decrease the contact resistance between the silicide layer and the local interconnection. However, since the very thin edge of the field oxide film surrounding the silicide layer is removed by the etching treatment, the junction within the semiconductor substrate comes to slightly appear after the removal of the very thin edge, resulting in the increased chance of causing junction leakage near the exposed surface.
Another technique for decreasing the contact resistance between the silicide layer and the local interconnection is described in the U.S. Pat. No. 5,190,893. In accordance with this technique, after formation of the silicide layer, a film for formation of a local interconnection is grown anew by making use of an appropriate material for improving the etching selectivity ratio thereof respective to the underlying silicide layer and patterned in the form of a local interconnection, followed by thermal treatment for nitrogenization in order to alloy the local interconnection with the underlying silicide layer, resulting in a decreased contact resistance.
In this case, although the contact resistance is certainly decreased, there is a possibility of accidentally increasing junction leakage of drain and source regions since the silicide layer tends to undergo reaction in nitrogen during the alloying process by thermal treatment.
As described above, while it is important to increase the etching ratio of a local interconnection more than that of the underlying silicide layer during patterning the local interconnection, it is effective for improving the selectivity ratio to make use of a material other than the silicide for forming the local interconnection. However, there is no report sufficiently discussing the technique to decrease the contact resistance between the silicide layer and the local interconnection without causing junction leakage at the periphery of the silicide layer.